The present invention generally relates to semiconductor integrated circuits, and more particularly, to the structure and formation of diffusion barrier structures that create insulation and prevent interdiffusion of copper.
An integrated circuit (IC) generally includes a semiconductor substrate in which a number of device regions are formed by diffusion or ion implantation of suitable dopants. This substrate usually involves a passivating and an insulating layer required to form different device regions. The total thickness of these layers is usually less than one micron. Openings through these layers (called vias or contact holes) allow electrical contact to be made selectively to the underlying device regions. A conducting material such as copper is used to fill these holes, which then make contact to the appropriate region of the semiconductor device.
The presence of a diffusion barrier, i.e., liner layer, on the sidewalls defining the openings is desirable because structural delamination and/or conductor metal diffusion can occur unless there is a layer of protection between the conductive layer and the etched insulating layer. For structural integrity, the liner layer should line the entire sidewall and generally cover the bottom surface of any vias as well.
By way of example, the resistance of copper used in interconnects increases exponentially as CMOS devices continue to be scaled down. This effect imposes substantial propagation delay on the microelectronic circuit. In the dielectric/liner/Cu scheme, several factors contribute to the high interconnect resistance for the 10 nm node and below: the high resistivity of the Cu liner and the increase of Cu resistivity due to surface and grain boundary electron scattering. Among these factors, liner resistance accounts for the major portion of interconnect resistance. For example, TaN is a common Cu barrier material and has a resistivity (˜300 μohm-cm) that is about 150 times higher than Cu resistivity. For 10 nm node and below, the presence of the liner layer reduces copper volume within the openings by approximately 30-50%. Therefore, further reducing liner resistivity is extremely important to reducing interconnect resistance, meeting interconnect resistance requirements, and improving device performance.